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lc 2 mos 8-/16-channel high performance analog multiplexers adg406/adg407/adg426 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1994C2010 analog devices, inc. all rights reserved. features 44 v supply maximum ratings v ss to v dd analog signal range low on resistance (80 maximum) low power fast switching t on < 160 ns t off < 150 ns break-before-make switching action applications audio and video routing automatic test equipment data acquisition systems battery powered systems sample hold systems communication systems avionics product highlights 1. extended signal range. 2. the adg406/adg407/adg426 are fabricated on an enhanced lc 2 mos process giving an increased signal range which extends to the supply rails. 3. low power dissipation. 4. low r on . 5. single/dual supply operation. 6. single supply operation. 7. for applications where the analog signal is unipolar, the adg406/adg407/adg426 can be operated from a single rail power supply. the parts are fully specified with a single +12 v power supply and remain functional with single supplies as low as +5 v. functional block diagrams 00026-001 s1 s16 a0 d a3 adg406 a1 a2 en 1 of 16 decoder figure 1. 00026-002 s1a s8b da adg407 s8a s1b db en a0 a1 a2 1 of 8 decoder figure 2. 00026-003 s1 s16 a0 d a3 adg426 a1 a2 en decoder/ latches wr rs figure 3.
adg406/adg407/adg426 rev. b | page 2 of 20 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? product highlights ........................................................................... 1 ? functional block diagrams ............................................................. 1 ? revision history ............................................................................... 2 ? general description ......................................................................... 3 ? specifications ..................................................................................... 4 ? dual supply ................................................................................... 4 ? single supply ................................................................................. 6 ? adg426 timing diagrams ..........................................................7 ? absolute maximum ratings ............................................................8 ? esd caution...................................................................................8 ? pin configurations and function descriptions ............................9 ? typical performance characteristics ........................................... 12 ? test circuits ..................................................................................... 15 ? terminology .................................................................................... 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 20 ? revision history 5/10rev. a to rev. b changes to ordering guide .......................................................... 20 6/09rev. 0 to rev. a updated format .................................................................. universal removed t grade ............................................................... universal added table 4 .................................................................................... 9 added table 6 .................................................................................. 10 added table 8 .................................................................................. 11 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 19 4/94revision 0: initial version
adg406/adg407/adg426 rev. b | page 3 of 20 general description the adg406, adg407, and adg426 are monolithic cmos analog multiplexers. the adg406 and adg426 switch one of sixteen inputs to a common output as determined by the 4-bit binary address lines: a0, a1, a2, and a3. the adg426 has on-chip address and control latches that facilitate microprocessor interfacing. the adg407 switches one of eight differential inputs to a common differential output as determined by the 3-bit binary address lines a0, a1 and a2. an en input on all devices is used to enable or disable the device. when disabled, all channels are switched off. the adg406/adg407/adg426 are designed on an enhanced lc 2 mos process that provides low power dissipation yet gives high switching speed and low on resistance. these features make the parts suitable for high speed data acquisition systems and audio signal switching. low power dissipation makes the parts suitable for battery powered systems. each channel conducts equally well in both directions when on and has an input signal range which extends to the supplies. in the off condition, signal levels up to the supplies are blocked. all channels exhibit break- before-make switching action preventing momentary shorting when switching channels. inherent in the design is low charge injection for minimum transients when switching the digital inputs.
adg406/adg407/adg426 rev. b | page 4 of 20 specifications dual supply v dd = +15 v 10%, v ss = ?15 v 10%, gnd = 0 v, unless otherwise noted. table 1. parameter 1 +25c ?40c to +85c unit test conditions/comments analog switch analog signal range v ss to v dd v r on 50 typ v d = 10 v, i s = ?1 ma 80 125 max v dd = +13.5 v, v ss = ?13.5 v r on match 4 typ v d = 0 v, i s = ?1 ma leakage currents v dd = +16.5 v, v ss = ?16.5 v source off leakage i s (off) 0.5 20 na max v d = 10 v, v s = + 10 v, see figure 26 drain off leakage i d (off) v d = 10 v, v s = + 10 v; see figure 27 adg406, adg426 1 20 na max adg407 1 20 na max channel on leakage i d , i s (on) v s = v d = 10 v; see figure 28 adg406, adg426 1 20 na max adg407 1 20 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 1 a max v in = 0 or v dd c in , digital input capacitance 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 120 ns typ r l = 300 , c l = 35 pf; v 1 = 10 v, v 2 = + 10 v; see figure 29 150 250 ns max break before make delay, t open 10 10 ns min r l = 300 , c l = 35 pf; v s = +5 v, see figure 30 t on (en, wr ) 120 175 ns typ r l = 300 , c l = 35 pf; v s = 5 v, see figure 31 160 225 ns max t off (en, rs ) 110 130 ns typ r l = 300 , c l = 35 pf; v s = 5 v, see figure 31 150 180 ns max adg426 only t w , write pulse width 100 ns min t s , address, enable setup time 100 ns min t h , address, enable hold time 10 ns min t rs , reset pulse width 100 ns min v s = +5 v charge injection 8 pc typ v s = 0 v, r s = 0 , c l = 1 nf; see figure 34 off isolation ?75 db typ r l = 1 k , f = 100 khz; v en = 0 v, see figure 35 channel-to-channel crosstalk 85 db typ r l = 1 k , f = 100 khz, see figure 36 c s (off ) 5 pf typ f = 1 mhz c d (off ) f = 1 mhz adg406, adg426 50 pf typ adg407 25 pf typ c d , c s (on) f = 1 mhz adg406, adg426 60 pf typ adg407 40 pf typ
adg406/adg407/adg426 rev. b | page 5 of 20 parameter 1 +25c ?40c to +85c unit test conditions/comments power requirements v dd = +16.5 v, v ss = ?16.5 v i dd 1 a typ v in = 0 v, v en = 0 v 5 a max i ss 1 a typ 5 a max i dd 100 a typ v in = 0 v, v en = 2.4 v 200 500 a max i ss 1 a typ 5 a max 1 temperature ranges is ?40c to +85c. 2 guaranteed by design, not subject to production test.
adg406/adg407/adg426 rev. b | page 6 of 20 single supply v dd = +12 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted. table 2. parameter 1 +25c ?40c to +85c unit test conditions/comments analog switch analog signal range 0 to v dd v r on 90 typ v d = +3 v, +8.5 v, i s = ?1 ma; 125 200 max v dd = +10.8 v leakage currents v dd = +13.2 v source off leakage i s (off ) 0.5 20 na max v d = 8 v/0.1 v, v s = 0.1 v/8 v; see figure 26 drain off leakage i d (off) v d = 8 v/0.1 v, v s = 0.1 v/8 v; see figure 27 adg406, adg426 1 20 na max adg407 1 20 na max channel on leakage i d , i s (on) v s = v d = 8 v/0.1 v, see figure 28 adg406, adg426 1 20 na max adg407 1 20 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inh 1 a max v in = 0 or v dd c in , digital input capacitance 8 pf typ f = 1 mhz dynamic characteristics 2 t transition 180 ns typ r l = 300 , c l = 35 pf; v 1 = 8 v/0 v, v 2 = 0 v/8 v; see figure 29 220 350 ns max break before make delay, t open 10 ns typ r l = 300 , c l = 35 pf; v s = 5 v, see figure 30 t on (en, wr ) 180 ns typ r l = 300 , c l = 35 pf; 240 350 ns max v s = +5 v, see figure 31 t off (en, rs ) 135 ns typ r l = 300 , c l = 35 pf; v s = 5 v, see figure 31 180 220 ns max adg426 only t w , write pulse width 100 ns min t s , address, enable setup time 100 ns min t h , address, enable hold time 10 ns min t rs , reset pulse width 100 ns min v s = +5 v charge injection 5 pc typ v s = 6 v, r s = 0 , c l = 1 nf; see figure 34 off isolation ?75 db typ r l = 1 k, f = 100 khz; see figure 35 channel-to-channel crosstalk 85 db typ r l = 1 k, f = 100 khz; see figure 36 c s (off ) 8 pf typ f = 1 mhz c d (off ) f = 1 mhz adg406, adg426 80 pf typ adg407 40 pf typ f = 1 mhz c d , c s (on) adg406, adg426 100 pf typ adg407 50 pf typ power requirements v dd = +13.2 v i dd 1 a typ v in = 0 v, v en = 0 v 5 a max i dd 100 a typ v in = 0 v, v en = 2.4 v 200 500 a max 1 temperature range is ?40c to +85c. 2 guaranteed by design, not subject to production test.
adg406/adg407/adg426 rev. b | page 7 of 20 adg426 timing diagrams 00026-009 50% 50% 2v 0.8v 3 v 0v 3v a 0, a1, a2, (a3) en 0v t w t s t h wr figure 4. timing sequence for latching the switch address and enable inputs figure 4 shows the timing sequence for latching the switch address and enable inputs. the latches are level sensitive; therefore, while wr is held low, the latches are transparent and the switches respond to the address and enable inputs. this input data is latched on the rising edge of wr . 00026-010 3 v 0v 0v 50% 50% t w rs t off (rs) switch output v 0 0.8v 0 figure 5. reset pulse width and reset turn off time figure 5 shows the reset pulse width, t rs , and the reset turn off time, t off ( rs ). note that all digital input signals rise and fall times are measured from 10% to 90% of 3 v; t r = t f = 20 ns.
adg406/adg407/adg426 rev. b | page 8 of 20 absolute maximum ratings t a = 25c unless otherwise noted. table 3. parameter rating v dd to v ss 44 v v dd to gnd ?0.3 v to +25 v v ss to gnd +0.3 v to ?25 v analog, digital inputs 1 v ss ? 2 v to v dd + 2 v or 20 ma, whichever occurs first continuous current, s or d 20 ma peak current, s or d 40 ma (pulsed at 1 ms, 10% duty cycle max) operating temperature range industrial (b version) ?40c to +85c storage temperature range ?65c to +150c junction temperature 150c plastic package ja , thermal impedance 75c/w lead temperature, soldering (10 sec) 260c plcc package ja , thermal impedance 80c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c ssop package ja , thermal impedance 122c/w lead temperature, soldering vapor phase (60 sec) 215c infrared (15 sec) 220c 1 overvoltages at a, s, d, wr , or rs will be clamped by internal diodes. current should be limited to the maximum ratings given. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adg406/adg407/adg426 rev. b | page 9 of 20 pin configurations and function descriptions v dd nc nc s16 d 28 v ss 27 s8 26 s7 25 s15 s14 s13 s6 24 s5 23 s4 22 s12 s3 21 s11 s2 20 s10 s1 19 s9 en 18 gnd a0 17 nc a1 16 a3 a2 15 nc = no connect adg406 top view (not to scale) 00026-004 1 2 5 6 7 8 9 10 11 12 14 13 3 4 figure 6. 28-lead pdip 1282726 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc = no connect s15 s14 s13 s12 s11 s10 s9 s7 s6 s5 s4 s3 s2 s1 s16 nc nc v dd d v ss s8 gnd nc a3 a2 a1 a0 en pin 1 indentfier adg406 top view (not to scale) 12 13 14 15 16 17 18 00026-005 figure 7. 28-lead plcc table 4. pin function descriptions pin no. neonic description 1 v dd most positive power supply potential. 2, 3, 13 nc no connect. 4 to 11 s16 to s9 source terminal 16 to source te rminal 9. these pins can be inputs or outputs. 12 gnd ground (0 v) reference. 14 to 17 a3 to a0 logic control input. 18 en active high digital input. when this pin is low, the device is disabled and all switches are turned off. when this pin is high, the ax logic inputs dete rmine which switch is turned on. 19 to 26 s1 to 8 source terminal 1 to source ter minal 8. these pins can be inputs or outputs. 27 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 28 d drain terminal. this pin ca n be an input or an output. table 5. truth table (adg406) a3 a2 a1 a0 en on sitch x x x x 0 none 0 0 0 0 1 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 1 5 0 1 0 1 1 6 0 1 1 0 1 7 0 1 1 1 1 8 1 0 0 0 1 9 1 0 0 1 1 10 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16
adg406/adg407/adg426 rev. b | page 10 of 20 v dd 1 db 2 nc 3 s8b 4 da 28 v ss 27 s8a 26 s7a 25 s7b 5 s6b 6 s5b 7 s6a 24 s5a 23 s4a 22 s4b 8 s3a 21 s3b 9 s2a 20 s2b 10 s1a 19 s1b 11 en 18 gnd 12 a0 17 nc 13 a1 16 nc 14 a2 15 nc = no connect adg407 top view (not to scale) 00026-006 figure 8. 28-lead pdip 1282726 234 5 6 7 8 9 10 11 25 24 23 22 21 20 19 nc = no connect s7b s6b s5b s4b s3b s2b s1b s7a s6a s5a s4a s3a s2a s1a s8b nc db v dd da v ss s8a gnd nc nc a2 a1 a0 en pin 1 indentfier adg407 top view (not to scale) 12 13 14 15 16 17 18 00026-007 figure 9. 28-lead plcc table 6. pin function descriptions pin no. neonic description 1 v dd most positive power supply potential. 2 db drain terminal b. this pin can be an input or an output. 3, 13, 14 nc no connect. 4 to 11 s8b to s1b source terminal 8b to source terminal 1b. these pins ca n be inputs or outputs. 12 gnd ground (0 v) reference. 15 to 17 a2 to a0 logic control input. 18 en active high digital input. when this pin is low, the device is disabled and all switches are turned off. when this pin is high, the ax logic inputs dete rmine which switch is turned on. 19 to 26 s1a to s8a source terminal 1a to source terminal 8a. these pins can be inputs or outputs. 27 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 28 da drain terminal a. this pin can be an input or an output. table 7. truth table (adg407) a2 a1 a0 en on sitch pair x x x 0 none 0 0 0 1 1 0 0 1 1 2 0 1 0 1 3 0 1 1 1 4 1 0 0 1 5 1 0 1 1 6 1 1 0 1 7 1 1 1 1 8
adg406/adg407/adg426 rev. b | page 11 of 20 00026-008 v dd 1 nc 2 3 s16 4 d 28 v ss 27 s8 26 s7 25 s15 5 s14 6 s13 7 s6 24 s5 23 s4 22 s12 8 s3 21 s11 9 s2 20 s10 10 s1 19 s9 11 en 18 gnd 12 a0 17 a1 16 13 a3 14 a2 15 nc = no connect adg426 top view (not to scale) wr rs figure 10. 28-lead pdip/ssop table 8. pin function descriptions pin no. mnemonic description 1 v dd most positive power supply potential. 2 nc no connect. 3 rs active low logic input. when this pin is low, all switches are open, and address and enable latches registers are cleared to 0. 4 to 11 s16 to s9 source terminal 16 to source te rminal 9. these pins can be inputs or outputs. 12 gnd ground (0 v) reference. 13 wr the rising edge of the wr signal latches the state of the address control lines and the enable line. 14 to 17 a3 to a0 logic control input. 18 en active high digital input. when this pin is low, the device is disabled and all switches are turned off. when this pin is high, the ax logic inputs dete rmine which switch is turned on. 19 to 26 s1 to s8 source terminal 1 to source te rminal 8. these pins ca n be inputs or outputs. 27 v ss most negative power supply potential. in single-supply applications, this pin can be connected to ground. 28 d drain terminal. this pin ca n be an input or an output. table 9. truth table (adg426) a3 a2 a1 a0 en wr rs on switch x x x x x 1 retains previous switch condition x x x x x x 0 none (a ddress and enable latches cleared) x x x x 0 0 1 none 0 0 0 0 1 0 1 1 0 0 0 1 1 0 1 2 0 0 1 0 1 0 1 3 0 0 1 1 1 0 1 4 0 1 0 0 1 0 1 5 0 1 0 1 1 0 1 6 0 1 1 0 1 0 1 7 0 1 1 1 1 0 1 8 1 0 0 0 1 0 1 9 1 0 0 1 1 0 1 10 1 0 1 0 1 0 1 11 1 0 1 1 1 0 1 12 1 1 0 0 1 0 1 13 1 1 0 1 1 0 1 14 1 1 1 0 1 0 1 15 1 1 1 1 1 0 1 16
adg406/adg407/adg426 rev. b | page 12 of 20 typical performance characteristics 150 0 ?15 15 ?10?50 510 120 90 60 30 00026-011 r on ( ? ) v d (v s ) (v) v dd = +15v v ss = ?15v v dd = +10v v ss = ?10v v dd = +12v v ss = ?12v v dd = +5v v ss =?5v t a = 25c figure 11. r on as a function of v d (v s ): dual supplies 100 0 ?15 15 ?10?50 510 80 60 40 20 00026-012 r on ( ? ) v d (v s ) (v) v dd = +15v v ss = ?15v 25c 125c 85c figure 12. r on as a function of v d (v s ) for different temperatures 0.10 ?0.02 ?15 15 ?10?50 510 0.06 0.08 0.04 0.02 0 00026-013 leakage current (na) v d (v s ) (v) v dd = +15v v ss = ?15v t a =+25c i d (off) i s (off) i d (on) figure 13. leakage currents as a function of v d (v s ) 400 0 01 2.5 5.0 7.5 10 12.5 200 250 300 350 150 100 50 00026-014 r on ( ? ) v d (v s ) (v) 5 t a = 25c v dd = +5v v ss =0v v dd = +10v v ss =0v v dd = +15v v ss = 0v v dd = +12v v ss =0v figure 14. r on as a function of v d (v s ): single supplies 150 0 01 246810 120 90 60 30 00026-015 r on ( ? ) v d (v s ) (v) 2 v dd = 12v v ss =0v 25c 125c 85c figure 15. r on as a function of v d (v s ) for different temperatures 0.02 ?0.02 01 246810 0.01 0 ?0.01 00026-016 leakage current (na) v d (v s ) (v) 2 v dd = +12v v ss =0v t a =+25c i s (off) i d (off) i d (on) figure 16. leakage currents as a function of v d (v s )
adg406/adg407/adg426 rev. b | page 13 of 20 100 0.1 100 1k 10k 100k 1m 10m 10 1 00026-017 i dd (ma) frequency (hz) v dd = +15v v ss = ?15v en = 2.4v en = 0v figure 17. positive supply current vs. switching frequency 160 60 1357911131 100 120 140 80 00026-018 t (ns) v in (v) 5 v dd = +15v v ss = ?15v t transition t on t off figure 18. switching time vs. v in (bipolar supply) 300 0 5 7 9 11 13 15 17 19 21 200 100 00026-019 t (ns) supply voltage (v) v in = +5v t transition t on t off figure 19. switching time vs. bipolar supply 100 0.0001 100 1k 10k 100k 1m 10m 0.01 0.1 1 10 0.001 00026-020 i ss (ma) frequency (hz) v dd = +15v v ss = ?15v en = 2.4v en = 0v figure 20. negative supply cu rrent vs. switching frequency 220 80 24681 0 120 140 160 180 200 100 00026-021 t (ns) v in (v) 1 2 v dd = +12v v ss =0v t transition t on t off figure 21. switching time vs. v in (single supply) 500 0 5 7 9 11 13 15 200 300 400 100 00026-022 t (ns) supply voltage (v) v in = +5v t transition t on t off figure 22. switching time vs. single supply
adg406/adg407/adg426 rev. b | page 14 of 20 140 40 100 1k 10k 100k 1m 10m 80 100 120 60 00026-023 off isolation (db) frequency (hz) v dd = +15v v ss = ?15v figure 23. off isol ation vs. frequency 140 40 100 1k 10k 100k 1m 10m 80 100 120 60 00026-024 crosstalk (db) frequency (hz) v dd = +15v v ss = ?15v figure 24. crosstalk vs. frequency
adg406/adg407/adg426 rev. b | page 15 of 20 test circuits 00026-025 s d v s v1 i ds r on = v1/i ds figure 25. on resistance 00026-026 s2 d v d s1 s16 en v dd v ss v dd v ss a v s +0.8v i s (off) figure 26. i s (off) 00026-027 s2 d v s s1 s16 en v dd v ss v dd v ss a v d +0.8v i d (off) figure 27. i d (off) 00026-028 d v s s1 s16 en v dd v ss v dd v ss a v d +2.4v i d (on) figure 28. i d (on) 00026-029 s1 d v dd v ss gnd v 1 a3 a2 a1 en adg426 1 1 similar connection for adg406/adg407 s16 r l 300 ? c l 35pf s2 thru s15 v 2 v out 2.4v 50 ? v in v ss v dd wr a0 rs 50% 50% 90% 90% t transition 3v address drive (v in ) t transition v out figure 29. switching time of multiplexer, t transition 00026-030 s1 d v dd v ss gnd a3 a2 a1 en adg426 1 1 similar connection for adg406/adg407 s16 r l 300 ? c l 35pf s2 thru s15 2.4v 50 ? v in v ss v dd wr a0 rs v s 0v output 3v address drive (v in ) t open 80% 80% v out figure 30. break-before-make delay, t open
adg406/adg407/adg426 rev. b | page 16 of 20 00026-031 s1 d v dd v ss gnd a3 a2 a1 en adg426 1 1 similar connection for adg406/adg407 r l 300 ? c l 35pf s2 thru s16 2.4v 50 ? v in v ss v dd wr a0 rs v s v out 90% 90% 3v t on (en) enable drive (v in ) 50% output 50% 0v 0v t off (en) v o figure 31. enable delay, t on (en), t off (en) 00026-032 s1 d v dd v ss gnd a3 a2 a1 en adg426 r l 300 ? c l 35pf s2 thru s16 2.4v v ss v dd wr a0 rs v s v out v wr v rs 0v 3v 50% 0v v 0 output 0.2v 0 wr t on (wr) figure 32. write turn-on time, t on ( wr ) 00026-033 s1 d v dd v ss gnd a3 a2 a1 en adg426 r l 300 ? c l 35pf s2 thru s16 2.4v v ss v dd a0 rs v s v out 0v 3v 50% 0v v 0 output 0.8v 0 rs t off (rs) wr v in figure 33. reset turn-off time, t off ( rs )
adg406/adg407/adg426 rev. b | page 17 of 20 00026-034 d v dd v ss gnd a3 a2 a1 en adg426 1 c l 1nf v ss v dd a0 rs v out wr 3v logic input (v in ) v out r s 2.4v v in s v s v out q inj = c l v out 1 similar connection for adg406/adg407. figure 34. charge injection 00026-035 s1 d v dd v ss gnd a3 a2 a1 en adg426 1 1 similar connection for adg406/adg407. r l 1k ? s16 2.4v v dd wr a0 rs v out v ss v in figure 35. off isolation 00026-036 d v dd v ss gnd a0 a1 a2 en adg426 1 1 similar connection for adg406/adg407. 1k ? 2.4v v dd wr a3 rs v out v ss s1 s16 v in s2 1k ? figure 36. crosstalk
adg406/adg407/adg426 rev. b | page 18 of 20 terminology v dd most positive power supply potential. v ss most negative power supply potential in dual supplies. in single supply applications, it may be connected to ground. gnd ground (0 v) reference. r on ohmic resistance between the d and s terminals. r on match difference between the r on of any two channels. i s (off) source leakage current when the switch is off. i d (off) drain leakage current when the switch is off. i d , i s (on) channel leakage current when the switch is on. v d (v s ) analog voltage on terminal d, terminal s. c s (off) channel input capacitance for off condition. c d (off) channel output capacitance for off condition. c d , c s (on) on switch capacitance. c in digital input capacitance. t on (en) delay time between the 50% and 90% points of the digital input and switch on condition. t off (en) delay time between the 50% and 90% points of the digital input and switch off condition. t transition delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. t open off time measured between 80% points of both switches when switching from one address state to another. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl (i inh ) input current of the digital input. crosstalk a measure of unwanted signal which is coupled through from one channel to another as a result of parasitic capacitance. off isolation a measure of unwanted signal coupling through an off channel. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. i dd positive supply current. i ss negative supply current.
adg406/adg407/adg426 rev. b | page 19 of 20 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole leads. compliant to jedec standards ms-011 071006-a 0.100 (2.54) bsc 1.565 (39.75) 1.380 (35.05) 0.580 (14.73) 0.485 (12.31) 0.022 (0.56) 0.014 (0.36) 0.200 (5.08) 0.115 (2.92) 0.070 (1.78) 0.050 (1.27) 0.250 (6.35) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.700 (17.78) max 0.015 (0.38) 0.008 (0.20) 0.625 (15.88) 0.600 (15.24) 0.015 (0.38) gauge plane 0.195 (4.95) 0.125 (3.17) 28 11 4 15 figure 37. 28-lead plastic dual in-line package {pdip} wide body (n-28-2) dimensions shown in inches and (millimeters) compliant to jedec standards mo-047-ab controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. 4 5 26 25 11 12 19 18 top view (pins down) sq 0.456 (11.582) 0.450 (11.430) 0.050 (1.27) bsc 0.048 (1.22) 0.042 (1.07) 0.048 (1.22) 0.042 (1.07) 0.495 (12.57) 0.485 (12.32) sq 0.021 (0.53) 0.013 (0.33) 0.430 (10.92) 0.390 (9.91) 0.032 (0.81) 0.026 (0.66) 0.120 (3.04) 0.090 (2.29) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.180 (4.57) 0.165 (4.19) bottom view (pins up) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier 042508-a figure 38. 28-lead plastic leaded chip carrier [plcc] (p-28) dimensions shown in inches and (millimeters)
adg406/adg407/adg426 rev. b | page 20 of 20 compliant to jedec standards mo-150-ah 060106-a 28 15 14 1 10.50 10.20 9.90 8.20 7.80 7.40 5.60 5.30 5.00 seating plane 0.05 min 0.65 bsc 2.00 max 0.38 0.22 coplanarity 0.10 1.85 1.75 1.65 0.25 0.09 0.95 0.75 0.55 8 4 0 figure 39. 28-lead shrink small outline package [ssop] (rs-28) dimensions shown in millimeters ordering guide model 1 temperature range package description package option 2 adg406bn ?40c to +85c 28-lead pdip n-28-2 adg406bnz ?40c to +85c 28-lead pdip n-28-2 adg406bp ?40c to +85c 28-lead plcc p-28 adg406bp-reel ?40c to +85c 28-lead plcc p-28 adg406bpz ?40c to +85c 28-lead plcc p-28 adg406bpz-reel ?40c to +85c 28-lead plcc p-28 adg407bn ?40c to +85c 28-lead pdip n-28-2 ADG407BNZ ?40c to +85c 28-lead pdip n-28-2 adg407bp ?40c to +85c 28-lead plcc p-28 adg407bp-reel ?40c to +85c 28-lead plcc p-28 adg407bpz ?40c to +85c 28-lead plcc p-28 adg407bpz-rl ?40c to +85c 28-lead plcc p-28 adg407bchips ?40c to +85c die adg426bn ?40c to +85c 28-lead pdip n-28-2 adg426bnz ?40c to +85c 28-lead pdip n-28-2 adg426brs ?40c to +85c 28-lead ssop rs-28 adg426brs-reel ?40c to +85c 28-lead ssop rs-28 adg426brs-reel7 ?40c to +85c 28-lead ssop rs-28 adg426brsz ?40c to +85c 28-lead ssop rs-28 adg426brsz-reel ?40c to +85c 28-lead ssop rs-28 1 z = rohs compliant part. 2 n = plastic dip, p = plastic leaded chip carrier (plcc), rs = shrink small outline package (ssop). ?1994C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d00026-0-5/10(b)

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